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Title: Implementation of 128-Bit Sparse Kogge-Stone Adder using Verilog


Implementation of 128-Bit Sparse Kogge-Stone Adder using Verilog
Author Name:
Geeta Rani, Asst. Prof. Sachin Kumar
Parallel Prefix adders have been one of the most notable among several designs proposed in the past. The advantage of utilizing the flexibility in implementing these structures based upon through put requirements. Due to continuing integrating intensity and the growing needs of portable devices, low power and high performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this proposed system, Kogge-Stone adder which is one of types of parallel prefix adder is used. Kogge stone is the fastest adder because of its minimum fan-out. When parallel prefix adder is compared with classical adders it is advantageous in every aspect. The study reveals that Parallel Prefix adder has the least power delay product when compared with its peer existing adder structures (Ripple carry adder, Carry save adders etc). Simulation results are verified using Xilinx 10.1 and MODELSIM 6.4a softwares.