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Volume & Issue no: Volume 4, Issue 3, March 2015

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Title:
VLSI Designing of High Speed Parallel Multiplier –Accumulator Based On Radix4 Booths Multiplier
Author Name:
Gaurav Pohane, Sourabh Sharma
Abstract:
ABSTRACT In this paper, we proposed a new architecture of multiplier-and-accumulator (MAC) for high-speed arithmetic. By combining multiplication with accumulation and devising a hybrid type of ripple carry adder (RCA), the performance was improved. Since the accumulator that has the largest delay in MAC was merged into RCA, the overall performance was elevated. Radix 4 modified Booth algorithms can be utilized for reduction of the partial products. The parallel multiplier like radix 4 modified booth multiplier accomplishes the computations utilizing fewer adders and less iterative steps. Based on the simplification of addition operation and power reduction property in ripple carry adder (RCA),a low power radix 4 modified booth multiplier is proposed, compared with the radix 4 modified booth multiplier using carry look ahead adder(CLA),the experimental result shows that our propose design has reduce the Delay of circuit to 6.21 % using RCA, Area has estimated as 947 which was 1141 when designed with CLA Adder. Keywords: Booth multiplier, Low power, Modified Booth Multiplier, Multiplication, Partial Product Generation (PPG), RCA, VHDL.
Cite this article:
Gaurav Pohane, Sourabh Sharma , " VLSI Designing of High Speed Parallel Multiplier –Accumulator Based On Radix4 Booths Multiplier" , International Journal of Application or Innovation in Engineering & Management (IJAIEM) , Volume 4, Issue 3, March 2015 , pp. 033-039 , ISSN 2319 - 4847.
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