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Volume & Issue no: Volume 4, Issue 1, January 2015

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Title:
A DFT technique for MCM (Multi Chip Module) testing
Author Name:
Prof.U.W.Kaware, Ms. Anushri Garud and Mr. Shubham Deshmukh
Abstract:
ABSTRACT Aggressive technology scaling has been the mainstay of integrated circuit design for the past 30 years. This is posing serious challenges to integrated circuit testing and its long term reliability. A major source of failures and test escapes in the integrated circuits can be attributed to timing only parametric failures. Products motivated by performance-driven or density-driven goals often use Multi-Chip Module (MCM) technology, even though it still faces several challenging problems that need to be resolved before it becomes a widely adopted technology. Among its most challenging problems is achieving acceptable MCM assembly yields while meeting quality requirements. This problem can be significantly reduced by adopting adequate MCM test strategies that is to guarantee the quality of incoming bare (unpackaged) dies prior to module assembly, to ensure the structural integrity and performance of assembled modules and to help isolate the defective parts and apply the repair process. In this paper today’s MCM test problems are described and the corresponding test and design-for-testability (DFT) strategies used for bare dies, substrates, and assembled MCMs are presented. Keywords: MCM testing, DFT, bare dies, substrate.
Cite this article:
Prof.U.W.Kaware, Ms. Anushri Garud and Mr. Shubham Deshmukh , " A DFT technique for MCM (Multi Chip Module) testing" , International Journal of Application or Innovation in Engineering & Management (IJAIEM) , Volume 4, Issue 1, January 2015 , pp. 093-100 , ISSN 2319 - 4847.
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