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Volume & Issue no: Volume 3, Issue 10, October 2014

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Title:
Design of Enhanced Hybrid Flip-Flop with Embedded Logic Module
Author Name:
G. V. G. KALYANI, B. UMASANKAR
Abstract:
ABSTRACT In this paper we propose a new kind of flip-flop which overcomes the disadvantages of static and dynamic flip-flop. We introduce a new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the pre-charge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The performance comparisons made in a TSMC025. Keywords:- DDFF, DDFF-ELM
Cite this article:
G. V. G. KALYANI, B. UMASANKAR , " Design of Enhanced Hybrid Flip-Flop with Embedded Logic Module" , International Journal of Application or Innovation in Engineering & Management (IJAIEM) , Volume 3, Issue 10, October 2014 , pp. 252-257 , ISSN 2319 - 4847.
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