Call of Papers for Current Volume **************** OnLine Submission of Paper

Volume & Issue no: Volume 3, Issue 10, October 2014

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Title:
Low Power Computing Logic Gates design using Reversible logic
Author Name:
p.Vanusha, k.Amurtha Vally
Abstract:
ABSTRACT Reversible logic has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its applications in low power CMOS design, cryptography, digital signal processing, optical information processing and nanotechnology. This paper presents a quantum cost efficient reversible full adder gate and Reversible Decoder in nanotechnology. This gate can work singly as a reversible full adder & Decoder unit and requires only one clock cycle. The proposed gate is a universal gate in the sense that it can be used to synthesize any arbitrary Boolean functions. To implement reversible logic gates we are designing Full adder and Decoder circuit by using the T-Spice simulation and calculate the power consumption with TSMC018 Nanometer Technology. Keywords :- Reversible logic, CMOS, Full adder,Decoder
Cite this article:
p.Vanusha, k.Amurtha Vally , " Low Power Computing Logic Gates design using Reversible logic" , International Journal of Application or Innovation in Engineering & Management (IJAIEM) , Volume 3, Issue 10, October 2014 , pp. 123-129 , ISSN 2319 - 4847.
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