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Title: DESIGN OF SDRAM MEMORY CONTROLLER USING AN OUT OF ORDER SCHEDULER FOR IMPROVING THROUGHPUT

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Title:
DESIGN OF SDRAM MEMORY CONTROLLER USING AN OUT OF ORDER SCHEDULER FOR IMPROVING THROUGHPUT
Author Name:
Shaik Mohammed Asheer, Dr.I.A.Pasha
Abstract:
SDRAMs are the most preferred form of memories for use as a System memory in SOCs due to their lower area compared to SRAMs. Memory controllers are used to perform the DRAM specific functions like Refresh, Activate and Precharge. A typical memory controller consists of a Command generator and a Scheduler. In this paper an out of order scheduler which will give higher priority for the requests which belong to the same row as the one that is currently activated. This will lead to less number of Activates and Precharges as compared to the first come first serve policy. The lesser number of Activates and Precharges will lead to a higher system memory throughput and contributes significantly to the improvement of system performance as memory is the bottleneck for high performance in any SOC.
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