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Title: DESIGN AND OPERATION OF PARALLEL CARRY-SAVE PIPELINED RSFQ MULTIPLIER FOR DIGITAL SIGNAL PROCESSING

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Title:
DESIGN AND OPERATION OF PARALLEL CARRY-SAVE PIPELINED RSFQ MULTIPLIER FOR DIGITAL SIGNAL PROCESSING
Author Name:
G.PRATHEEPA, D.MAHESH KUMAR
Abstract:
We have developed and experimentally evaluated at high -speed a complete set of arithmetic circuits (multiply, add, and accumulate) for high performance digital signal processing (DSP). These circuits take advantage of the unique features of the Rapid Single -Flux Quantum (RSFQ) logic/memory family, including fusion of logic and memory functions at the gate level, pulse representation of clock and data, and the ability to maintain inter cell propagation delays using Josephson transmission lines (JTLs). The circuits developed have been successfully used in the implementation of a serial radix 2 butterfly, a decimation digital filter, and of an arithmetic unit for digital beam forming. The 8×8-bit RSFQ multiplier uses a two - level parallel carry - save reduction tree that significantly reduces the multiplier latency. The 80-GHz carry-save reduction is implemented with asynchronous data -driven wave pipelined [4:2] compressors built with toggle flip-flop cells. The design has mostly regular layout with both local and global connections between modules
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